1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming an isolation region on a substrate of semiconductor device.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. In a dynamic random access memory (DRAM) device, for example, the field effect transistors (FETs) are isolated from each other by isolation regions in order to prevent current leakage among the FETs. Conventionally, local oxidation of silicon (LOCOS) technique is widely utilized in semiconductor industry to provide isolation regions among the various devices in the substrate. Since the LOCOS technique has been used for some time, it is one of the most reliable and low cost methods for fabricating device isolation regions. However, there are still some drawbacks of the LOCOS. The drawbacks include internal stress generation and bird""s beak encroachment. For a highly integrated circuit, the problem of the bird""s beak encroachment by the isolation regions is especially difficult to avoid, thus isolation regions cannot effectively isolate devices.
Shallow trench isolation (STI) technique is also a common conventional method of forming isolation regions. Shallow trench isolation is formed by first anisotropically etching to form a trench in the substrate, and then depositing oxide in the trench to form an isolation region having its top surface level with the substrate surface.
FIGS. 1A through 1D are schematic, cross-sectional views showing a conventional method of fabricating a shallow trench isolation.
In FIG. 1A, a pad oxide layer 102 is formed on a substrate 100. A silicon nitride layer 104 is formed on the pad oxide layer 102 by using chemical vapor deposition. A patterned photoresist layer 106 is formed on the silicon nitride layer 104.
In FIG. 1B, the patterned photoresist layer 106 is used as a mask. The silicon nitride 104, the pad oxide layer 102, and the substrate 100 are etched by a conventional photolithography process. A trench 108 is formed in the substrate 100. The patterned photoresist layer 106 is removed.
In FIG. 1C, a thermal oxidation is performed. A liner oxide layer 110 is formed on the sidewall of the trench 108 and conformal to the trench 108. An oxide layer 112 is formed over the substrate 100 to fill the trench 108 by using atmospheric pressure chemical vapor deposition.
In FIG. 1D, a densification process is performed to densify the oxide layer 112 at a temperature of about 1000xc2x0 C. for about 10 minutes to 30 minutes to turn the oxide layer 112 into a compact layer. The silicon nitride layer 104 is used as an etching stop layer. A portion of the oxide layer 112 on the silicon nitride layer 104 is removed by chemical-mechanical polishing (CMP). An oxide plug 112a is formed in the trench 108. However, slurry used during the CMP step easily scratches the oxide layer 112. Therefore, micro-scratches 114 easily occur in the surface of oxide plug 112a during performing chemical-mechanical polishing.
In FIG. 1E, a hot phosphoric acid (H3PO4) is used to remove the silicon nitride layer 104. Then, a hydrofluoric (HF) dip step is performed to remove the pad oxide layer 102. Therefore, a oxide plug 112b is formed in the substrate 100.
In the conventional process, the micro-scratches 114 generated during the CMP step become deep scratches 116 after the HF dip step. According to the experimental data, the scratches 116 may even have a depth of about 0.1 m. Polysilicon layers (not shown) easily fill the scratches 116 in the following process of forming metal oxide semiconductor (MOS) transistors. The polysilicon layer filling the scratches 116 are difficult to remove in the step of patterning the polysilicon layers. The remaining polysilicon layers thus easily connect with neighboring active regions beside shallow trench isolation and give rise to device shorts.
It is therefore an objective of the present invention to provide a method of forming a shallow trench isolation that prevents device shorts due to micro-scratches from happening.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, this invention provides a method of fabricating a shallow trench isolation. The method performs a densification process after performing chemical-mechanical polishing on an isolation plug. The isolation plug becomes compact after the densification process. Thus, the isolation plug can prevent micro-scratches from forming deep scratches so that shorts due to the micro-scratches do not happen.
The invention of fabricating a shallow trench isolation includes the following steps. A pad oxide layer is formed on a substrate. A mask layer and a photoresist layer are formed in sequence over the substrate. A photolithography process is performed. The photoresist layer is used as an etching mask. The mask layer, the pad oxide layer, and the substrate are patterned. A trench is formed in the substrate. A liner oxide layer is formed on the substrate exposed by the trench by thermal oxidation. An isolation layer fills in the trench. A densification process is performed on the isolation layer. The isolation layer on the pad layer is removed by chemical-mechanical polishing. Then, a post-CMP densification process is performed. Sequentially, the mask layer and the pad oxide layer are removed by wet etching to form an isolation plug.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the present invention as claimed.